Silicon Semiconductor

Closing the gap: How intelligent sensing is reshaping wafer process control

Here, Vidya Vijay, Director of Business Development at Nordson Test and Inspection, examines how intelligent in-situ sensing ...
Nanowerk

Ion-beam origami unlocks wafer-scale 3D photonic systems

Broad-beam ion etching folds flat nanostructures into 3D photonic devices across a 4-inch wafer while preserving speed, uniformity, and optical function. (Nanowerk Spotlight) 3D photonic devices face ...
Semiconductor Engineering

Microchip Manufacturing: Understanding The Semiconductor Manufacturing Process

Over the past several decades, the semiconductor industry has experienced sustained growth. Early expansion was driven by the ...
Electronics Weekly

Imec develops die-to-wafer bond process with 2µm pad pitch

Imec has developed a Cu-to-Cu and SiCN-to-SiCN die-to-wafer bonding process resulting in a Cu bond pad pitch of only 2µm at <350nm die-to-wafer overlay error, achieving good electrical yield. Such ...
ExtremeTech

TSMC Announces New System-on-Wafer Process With 3D-Stacking

Share on Facebook (opens in a new window) Share on X (opens in a new window) Share on Reddit (opens in a new window) Share on Hacker News (opens in a new window) Share on Flipboard (opens in a new ...
Electronic Design

Ring-Oscillator Process Monitors for Wafer-Level CMOS Screening

Ring-oscillator process monitors give production test teams a fast on-die frequency measurement for identifying CMOS process variation and sorting dies at wafer level. A process monitor is a dedicated ...
pv magazine International

Upgrades needed to process larger wafers, says VDMA

In an update to its International Technology Roadmap for Photovoltaics, German engineering association the VDMA notes standardization of wafer size is a topic of great interest to the country’s PV ...